The present invention relates to electronic circuits and applications and method of manufacture thereof. More specifically, the invention relates to a hybrid transistor circuit incorporating charge storage molecules.
The discussion of any work, publications, sales, or activity anywhere in this submission, including in any documents submitted with this application, shall not be taken as an admission by the inventors that any such work constitutes prior art. The discussion of any activity, work, or publication herein is not an admission that such activity, work, or publication was known in any particular jurisdiction.
The great majority of electronic devices in use today employ solid-state transistors as a chief building block. In digital devices, and in many analog devices, these transistors are field-effect transistors (FETs) of various types and used in various configurations.
One important goal in the development of electronic devices is miniaturization. The smaller the individual transistor device, the more complex and powerful the electronic circuit that can be constructed in a given area. However, an alternative to miniaturization is multi-mode operation. Thus, if a transistor with just two state operation is replaced with a transistor with four or eight state operation, even of the same size, again more complex and highly functional circuits can be constructed in a given region.
A further goal in the development of electronic devices is devices that can retain state when power is OFF. This is particularly true for devices such as memory elements used in cell-phones. A device widely used in such appliances is FLASH memory. FLASH memory, as known in the art, commonly employs one or more floating gate FETs to hold charge.
However, there are at least two drawbacks to commonly used FLASH memories. One is that current manufacturing technologies are expected to provide limited ability to shrink memory cells thereby limiting memory density. The other is that many FLASH memory designs require high-power (as much as 15 V) to write to the memory.
Multibit storage has been proposed for various types of FLASH memory cells in order to increase memory density. However, most current approaches have been accompanied by many problems, such as: (1) limited precision in reading, i.e., the inability to detect the current with sufficiently high accuracy and high speed; (2) inaccurate writing, i.e., the inability to place the right amount of charge on the floating gate to obtain the target VT (threshold voltage) value; (3) unreliability due to lack of maintenance of adequate spacing between adjacent stored levels in a memory cell for sufficiently long time intervals.
In a conventional FLASH, the threshold voltage depends analogically on the amount of charge stored in the floating gate and hence the IDS can be changed over a large range of values. In such devices, if multiple bits are desired, the xcex94IDS between states becomes smaller which in turn makes the sensing and writing prone to errors. To avoid this problem, the xcex94IDS between bits can be increased; however, this is generally at the cost of higher voltages, which can degrade reliability and make devices more difficult to operate.
Single-electron memories have recently been investigated for replacement of DRAM memories. These devices consist of a transistor where small metal or semiconductor islands are placed in the SiO2 matrix. These islands exhibit coulomb blockade oscillations and can therefore be used as multi-value memories. Although several single-electron memory approaches have been reported, they all require that the islands be in the nanoscale regime in order to observe oscillations. Because all the reported devices are fabricated using non-manufacturable shrinking techniques, they all suffer from non-reproducibility, owing to the variation in the island size from device to device. The variation of size, orientation, and charge state may ultimately limit the viability of using single-electron charging for memory applications. Moreover, these single-electron charging devices still require high voltages (generally  greater than 15 V) to store multiple levels.
Various strategies have been proposed for constructing memory devices using molecular electrical storage elements, among them those discussed in the below indicated patents and other publications:
U.S. Pat. No. 6,272,038; High-density non-volatile memory devices incorporating thiol-derivatized porphyrin trimers
U.S. Pat. No. 6,212,093; High-density non-volatile memory devices incorporating sandwich coordination compounds
U.S. Pat. No. 6,208,553; High density non-volatile memory device incorporating thiol-derivatized porphyrins.
Strategies and background techniques for using a dummy gate in constructing a semiconductor device are discussed in:
U.S. Pat. No. 5,960,270; Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions.
[1] K. M. Roth, N. Dontha, R. B. Dabke, D. T. Gryko, C. Clausen, J. S. Lindsey, D. F. Bocian, and Werner G. Kuhr, xe2x80x9cMolecular Approach toward Information Storage Based on the Redox Properties of Porphyrins in Self-Assembled Monolayers,xe2x80x9d J. Vac. Sci. Technol. B 2000, 18, 2359-2364.
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The present invention involves a novel hybrid transistor circuit that includes charge storage molecules as described here in the dielectric region of a FET. These storage molecules, in specific embodiments, can be made to hold charge and thus allow a hybrid transistor according to specific embodiments of the present invention to operate analogously to a floating gate FET. This device will at times be referred to herein as a molecular-FET or m-FET.
In further specific embodiments, an m-FET can have molecules that store discrete (or quantized) amounts of charge, thus allowing an m-FET to have multi-state operation.
In further specific embodiments, the invention involves a memory cell that operates similarly to a FLASH-type memory cell. This cell can be based on an m-FET and is referred to at times herein as a molecular-hybrid memory cell.
According to specific embodiments of the invention, a molecular-hybrid memory cell has one or more of the following advantages: (1) low power and/or voltage operation (can be less than about 2V) and/or low power consumption, (2) in specific constructions, allows for multi-valued memory operation due to the discrete states of the molecules, (3) in particular constructions, allows for straightforward fabrication of charge molecules via self-assembly approaches, (4) fault-tolerance through the use of multiple molecules in a given memory device, (5) for DRAM-type devices, charge-retention times of up to several minutes (for example, greater than 1,000 times that of certain semiconductor memories), and (6) scalability down to molecular dimensions.
In specific embodiments, the invention can be used in a memory device that has some operating characteristics analogous to a floating gate Si-MOSFET or a FLASH memory, but with the differences and advantages discussed herein. An Si-MOSFET, as known in the art, generally comprises (1) source, (2) drain, and (3) channel regions, with the channel region separated by (4) a non-conducting layer (e.g., a dielectric layer) from (5) a control gate. Modified MOSFET""s, designed for storage of data in some types of FLASH memory are known that include (6) a floating gate between the control gate (which, particularly in floating gate designs is sometimes referred to as a counter electrode) and the channel region, generally embedded in the dielectric layer. In such designs, the floating gate can be injected with current to hold charge after disconnection of the control gate from a voltage or current source.
According to specific embodiments of the present invention, some or all of the dielectric layer of a MOSFET-type device is replaced by molecular components. At a minimum, these components include charge-storage molecule(s) (CSM), e.g., porphyrin(s) or porphyrinic molecule(s) or other charge storage molecule(s) as described herein and in the incorporated references. In certain embodiments, the charge-storage molecule is attached to a substrate via a linker, also termed a channel linker, as described herein and in the incorporated references. In specific embodiments, a control-gate spacer is placed between the distal end (the end furthest away from the channel region) of the charge-storage molecule in order to discourage electron transfer across the control gate-charge-storage molecule interface and to enhance stored charge imaging in the channel region.
In specific embodiments, the charge storage molecules and associated molecules are placed in the dielectric region along with an electrolyte. A control gate is placed over the molecular components.
In certain preferred embodiments, the charge storage molecules comprising the molecular layer of an m-FET are porphyrinic macrocycles, and more preferably are porphyrins. One advantage of porphyrinic macrocycles is the ability to design porphyrinic macrocycles having a plurality of different and distinguishable non-zero oxidation states (charge states), thus allowing multi-state operation in specific embodiments. For example, in an m-FET, multi-valued memory operation can significantly increase memory density.
It will be understood by those of skill in the art that devices constructed according to the teachings provided herein can be made to behave analogously to a floating gate FLASH memory device. A method of operation of such a device according to specific embodiments of the invention proceeds as follows: during a write process, an appropriate voltage is applied to the gate; this voltage oxidizes the molecule(s) (e.g., electron(s) tunnel out) and stores charge on the molecule(s); this stored charge is then used to alter the threshold voltage of the m-FET, e.g., a positive charge on the molecule(s) will result in a negative shift in threshold voltage (in present embodiments, molecules are generally cation-based, although other embodiments are possible in which CSM can hold a negative charge, resulting in a positive shift in threshold voltage); this altered threshold voltage is sensed in order to determine the data stored on the m-FET.
The invention and various specific aspects and embodiments will be better understood with reference to the following drawings and detailed descriptions. For purposes of clarity, this discussion refers to devices, methods, and concepts in terms of specific examples. However, the invention and aspects thereof may have applications to a variety of types of devices and systems. It is therefore intended that the invention not be limited except as provided in the attached claims.
Furthermore, it is well known in the art that logic systems and methods such as described herein can include a variety of different components and different functions in a modular fashion. Different embodiments of the invention can include different mixtures of elements and functions and may group various functions as parts of various elements. For purposes of clarity, the invention is described in terms of systems that include many different innovative components and innovative combinations of innovative components and known components. No inference should be taken to limit the invention to combinations containing all of the innovative components listed in any illustrative embodiment in this specification.
All references, publications, patents, and patent applications cited herein are hereby incorporated by reference in their entirety for all purposes.